The present invention relates to generating clock signals with different phases, and more particularly, to a clock generator (e.g., an injection-locked phase rotator) using resistive components to generate sub-gate delays and/or using a common-mode voltage based frequency-locked loop circuit for frequency offset reduction.
Many electronic systems include one or more synchronous components that rely on receiving related signals at substantially the same time to maintain proper operating characteristics of the electronic system. In some cases, data transfer between system components may be synchronized by one or more clock signals originating from a common source. The system components may receive the clock signals through a clock network, which may include clock generation and distribution circuits. Hence, there is a need for a clock generator that is capable of generating the clock signals with fine phase steps for accurate timing control in various electronic applications.